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| ga20sicp 12- 263 nov 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - modules - copack/ pg 1 of 12 normally ? off silicon carbide junction transistor features package ? 175 c maximum operating t emperature ? gate oxide free sic s witch ? optional gate return pin ? exceptional safe operating area ? integrated sic schottky rectifier ? excellent gain linearity ? temperature independent s witchi ng p erformance ? low output capacitance ? positive temperature coefficient of r ds,on ? suitable for connecting an anti - parallel d iode ? r ohs compliant 7l d2pak (to - 263 - 7l) advantages applications ? compatible with si mosfet/igbt gate drive ics ? > 20 s short - circuit withstand capability ? lowest - in - class conduction losses ? high circuit efficiency ? minimal input signal distortion ? high amplifier bandwidth ? down hole oil drilling, geothermal instrumentation ? hybrid electric vehicles (hev) ? solar inverters ? switched - mode power supply (smps) ? power factor correction (pfc) ? induction heating ? uninterruptible power supply (ups) ? motor drives table of contents section i: absolute maximum ratings ................................ ................................ ................................ .......... 1 section ii: static electrical characteristics ................................ ................................ ................................ ... 2 section iii: dynamic electrical characteristics ................................ ................................ ............................ 2 section iv: figures ................................ ................................ ................................ ................................ .......... 4 section v: driving the ga20sicp12 - 263 ................................ ................................ ................................ ....... 8 section vi: package dimensions ................................ ................................ ................................ ................. 12 section vii: spice model parameters ................................ ................................ ................................ ......... 1 3 section i: absolute maximum ratings parameter symbol conditions value unit notes drain ? source voltage v ds v gs = 0 v 12 00 v continuous drain current i d t c = 2 5c 45 a fig. 17 continuous drain current i d t c = 14 5c 2 0 a fig. 17 continuous gate current i g 1 .3 a continuous gate return current i gr 1.3 a turn - off safe operating area rbsoa t vj = 175 o c, clamped inductive load i d,max = 20 @ v ds v dsmax a fig. 19 short circuit safe operating area scsoa t vj = 175 o c, i g = 1 a , v ds = 8 00 v, non repetitive >20 s reverse gate ? source voltage v sg 30 v reverse drain ? source voltage v sd 25 v power dissipation p tot t c = 2 5 c / 145 c , t p > 100 ms 282 / 56 w fig. 16 storage temperature t stg - 55 to 175 c 1 g tab drain 2 gr 3 s 4 s 5 s 6 s 7 s drain (tab) source (pin 3, 4, 5, 6, 7) gate (pin 1) gate return (pin 2) v ds = 12 00 v r ds(on) = 5 0 m i d (@ 25 c ) = 45 a i d (@ 14 5c ) = 20 a h fe (@ 25c ) = 80 please note: the source and gate return pins are not exchangeable. their exchange might lead to malfunction.
ga20sicp 12- 263 nov 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - modules - copack/ pg 2 of 12 parameter symbol conditions value unit notes free - w heeling sic diode repetitive peak reverse voltage v rrm 1200 v continuous forward current i f t c 11 0 c 20 a rms forward current i f(rms) t c 1 10 c 32 a surge non - repetitive forward current, half sine wave i f sm t c = 25 c, t p = 10 ms t c = 1 50 c, t p = 10 ms 65 55 a non - repetitive peak forward current i f,max t c = 25 c, t p = 10 s 280 a i 2 t value i 2 dt t c = 25 c, t p = 10 ms t c = 11 5 c, t p = 10 ms 21 15 a 2 s thermal characteristics thermal resistance, junction - case r thjc sic junction transistor 0.53 c/w fig. 20 thermal resistance, junction - case r thjc sic diode 0.8 c/w fig. 21 section ii: static electrical characteristics a: on state b: off state section iii: dynamic electrical characteristics a: capacitance and gate charge parameter symbol conditions value unit notes min. typical max. drain ? source on r esistance r ds(on) i d = 20 a, t j = 25 c i d = 2 0 a, t j = 1 5 0 c i d = 2 0 a, t j = 175 c 5 0 83 9 5 m fig. 4 gate ? source saturation voltage v gs,sat i d = 20 a, i d /i g = 40 , t j = 25 c i d = 20 a, i d /i g = 30 , t j = 175 c 3.44 3.24 v fig. 7 dc current gain h fe v ds = 8 v, i d = 2 0 a , t j = 25 c v ds = 8 v, i d = 2 0 a , t j = 12 5 c v ds = 8 v, i d = 2 0 a , t j = 17 5 c 80 51 4 5 ? fwd forward voltage v f i f = 20 a, t j = 25 c i f = 20 a, t j = 175 c 2.2 4.4 v drain leakage current i dss v ds = 12 00 v, v gs = 0 v, t j = 25 c v ds = 12 00 v, v gs = 0 v, t j = 1 50 c v ds = 12 00 v, v gs = 0 v, t j = 17 5 c 1 0 20 4 0 a fig. 8 gate leakage current i s g v sg = 2 0 v, t j = 25 c 20 na parameter symbol conditions value unit notes min. typical max. input capacitance c is s v gs = 0 v, v d s = 8 00 v, f = 1 mhz 2870 pf fig. 9 reverse transfer/output capacitance c rss /c oss v ds = 1 v, f = 1 mhz v ds = 400 v, f = 1 mhz v ds = 800 v, f = 1 mhz 1260 115 85 pf fig. 9 total output capacitance charge qoss v ds = 400 v v ds = 800 v 85 125 nc output capacitance stored energy e oss v gs = 0 v, v ds = 800 v, f = 1 mhz 35 j fig. 10 effective output capacitance, time related c os s ,tr i d = constant, v gs = 0 v, v ds = 0?800 v 155 pf effective output capacitance, energy related c os s ,er v gs = 0 v, v ds = 0?800 v 110 pf gate - source charge q gs v gs = - 5?3 v 2 5 nc gate - drain charge q gd v gs = 0 v, v ds = 0?800 v 80 nc gate charge - total q g 10 5 nc ga20sicp 12- 263 nov 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - modules - copack/ pg 3 of 12 b: switching 1 1 ? all times are relative to the drain - source voltage v ds parameter symbol conditions value unit notes min. typical max. internal gate resistance ? on r g(int - on) v gs > 2 . 5 v , v ds = 0 v, t j = 17 5 oc 0.13 turn o n delay time t d(o n ) t j = 25 oc, v ds = 8 00 v, i d = 2 0 a, resistive load refer to section v for additional driving information. 12 ns fall time , v ds t f 1 4 ns fig. 11 , 13 turn o ff delay time t d(o ff ) 2 4 ns rise time , v ds t r 1 2 ns fig. 12 , 14 turn o n delay time t d(o n ) t j = 17 5 oc, v ds = 8 00 v, i d = 2 0 a, resistive load 15 ns fall time , v ds t f 13 ns fig. 11 turn o ff delay time t d(o ff ) 30 ns rise time , v ds t r 1 0 ns fig. 12 turn - on energy per pulse e on t j = 25 oc, v ds = 8 00 v, i d = 2 0 a, inductive load refer to section v . 320 j fig. 11 , 13 turn - off energy per pulse e off 4 0 j fig. 12 , 14 total switching energy e t ot 3 60 j turn - on energy per pulse e on t j = 17 5 oc, v ds = 8 00 v, i d = 2 0 a, inductive load 300 j fig. 11 turn - off energy per pulse e off 30 j fig. 12 total switching energy e t ot 330 j ga20sicp 12- 263 nov 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - modules - copack/ pg 4 of 12 section iv: figures a: static characteristic s figure 1: typical output characteristics at 25 c figure 2 : typi cal output characteristics at 1 50 c figure 3 : typical output characteristics at 175 c figure 4: dc current gain vs. drain current figure 5: on - resistance vs. gate current figure 6 : on - resistance vs. temperature ga20sicp 12- 263 nov 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - modules - copack/ pg 5 of 12 figure 7: typical gate ? source saturation voltage figure 8: typical blocking characteristics b: dynamic characteristic s figure 9: input, output, and reverse transfer capacitance figure 10: energy stored in output capacitance figure 11 : typical switching times and turn on energy losses vs. temperature figure 12 : typical switching times and turn o ff energy losses vs. temperature ga20sicp 12- 263 nov 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - modules - copack/ pg 6 of 12 figure 13 : typical switching times and turn on energy losses vs. drain current figure 14 : typical switching times and turn o ff energy losses vs. drain current c: current and power derating figure 15 : typical hard switched device power loss vs. switching frequency 2 figure 16: power derating curve figure 17 : drain current derating vs. temperature figure 18: forward bias safe operating area at t c = 25 o c 2 ? representative values based on device conduction and switching loss. actual losses will depend on gate drive conditions, device load, and circuit topology. ga20sicp 12- 263 nov 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - modules - copack/ pg 7 of 12 figure 19 : turn - off safe operating area figure 20: sjt transient thermal impedance figure 21: fwd transient thermal impedance figure 22: typical fwd forward characteristics ga20sicp 12- 263 nov 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - modules - copack/ pg 8 of 12 section v: driving the ga20sicp12 -263 drive topology gate drive power consumption switching frequency application emphasis availability ttl logic high low wide temperature range coming soon constant current medium medium wide temperature range coming soon high speed ? boost capacitor medium high fast switching production high speed ? boost inductor low high ultra fast switching coming soon proportional lowest high wide drain current range coming soon pulsed power medium n/a pulse power coming soon a: static ttl logic driving the ga20sicp12 - 263 may be driven with direct (5 v) ttl logic and current amplification. the amplified current level of the supply must meet or exceed the steady state gate current (i g,steady ) required to operate the ga20sicp12 - 263. minimum i g,steady is dependent on the anticipated drain current i d through the sjt and the dc current gain h fe , it may be calculated from the following equation. an accurate value of the h fe may be read from figure 4 . an optional resistor r g may be used in ser ies with the gate pin to trim i g,steady , also an optional capacitor c g may be added in parallel with r g to facilitate faster sjt switching if desired, further details on these options are given in the following section. ? ? , ?????? ? ? ? ?? ( ? , ? ? ) ? 1 . 5 figure 23 : ttl gate drive schematic b: high speed driving the sjt is a current controlled transistor which requires a positive gate current for turn - on and to remain in on - state. an idealized gate current waveform for ultra - fa st switching of the sjt while maintaining low gate drive losses is shown in figure 24 , it features a positive current peak during turn - on, a negative current peak during turn - off, and continuous gate current during on - state. figure 24 : an idealized gate current waveform for fast switching of an sjt. an sjt is rapidly switched from its blocking state to on - state when the neces sary gate charge, q g , for turn - on is supplied by a burst of high gate current, i g,on , until the sjt gate - source capacitance, c gs , and gate - drain capacitance, c gd , are fully charged. ? ?? = ? ? , ?? ? ? 1 ? ?? ? ?? + ? ?? ttl gate signal 5 / 0 v ttl i/p 5 v d s g gr c g r g i g,steady ga20sicp 12- 263 nov 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - modules - copack/ pg 9 of 12 ideally, i g,on should terminate when the drain voltage falls to its on - state value in order to avoid unnecessary drive losses during the steady on - state. in practice, the rise time of the i g,on pulse is affected by the parasitic inductances, l par in the device package and drive circuit. a voltage developed across the parasitic inductance in the source path, l s , can de - bias the gate - source junction, when high drain currents begin to flow through the device. the voltage applied to the gate pin should be maintained high enough, above the v gs ,sat (see figure 7 ) level to counter these effects. a high negative peak current, - i g,off is recommended at the start of the turn - off transition, in order to rapidly sweep out the injected carriers from the gat e, and achieve rapid turn- off. turn off can be achieved with v gs = 0 v, however a negative gate voltage v gs may be used in order to speed up the turn - off transition. gate return pin the optional gate return (gr) pin allows for a reduction of source path i nductive and resistive coupling in the gate driver connection to the ga20sicp12 - 263 . drain currents through the source pin during transient and steady state operation induce an undesirable source voltage in all power transistors due to unavoidable source p in inductance and resistance. this voltage can negatively affect gate driving performance, however the gate return pin allows for decoupling from these source current path effects which results in faster switching an d higher efficiency gate driving. b:1: high s peed, low loss drive with boost capacitor, ga03iddjt30 - fr4 the ga20sicp12 - 263 may be driven using a high speed, low loss drive with boost capacitor topology in which multiple voltage levels, a gate resistor, and a gate capacitor are used to provide fast sw itching current peaks at turn - on and turn - off and a continuous gate current while in on - state. a 3 kv isolated evaluation gate drive board ( ga03iddjt30 - fr4 ) utilizing this topology is commercially available for high and low - side driving, its datasheet provides additional details about this drive topology. figure 25 : topology of the ga03iddjt30- fr4 two voltage source gate driver. the ga03iddjt30 - fr4 evaluation board comes equipped with two on board gate drive resistors (rg1, rg2) pre - installed for an effective gate resistance 3 of rg = 3.75 ?. it may be necessary for the user to reduce rg1 and rg2 under high drain current conditions for safe operation of the ga20sicp12 - 263. the steady state current supplied to the gate pin of the ga20sicp12 - 263 with on - board rg = 3.75 ?, is shown in figure 26 . the maximum allowable safe value of rg for the user?s required drain current can be read from figure 27 . for the ga20sicp12 - 263, r g must be reduced for i d ~ 15 a for safe operation with the ga03iddjt30 - fr4 . for operation at i d ~ 15 a, r g may be calculated from the following equation, which contains the dc current gain h fe and the gate - source saturation voltage v gs,sat ( figure 7 ) . ? ? , ??? = ? 4 . 7 ? ? ? ?? , ??? ? ? ? ?? ( ? , ? ? ) ? ? ? 1 . 5 ? 0 . 6 i g cg2 gate signal v gh d1 r4 r1 u1 v gl v ee u2 v gl v ee v gl u3 v gh u4 v ee c2 c1 v ee u5 v gl v ee u6 cg1 rg1 rg2 r2 r3 c5 c3 c4 c8 c6 c9 c10 +12 v +12 v vcc high vcc high rtn vcc low vcc low rtn signal signal rtn gate source voltage isolation barrier ga03iddjt30-fr4 gate driver board d s g gr ga20sicp 12- 263 nov 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - modules - copack/ pg 10 of 12 figure 26 : typical steady state gate current supplied by the ga03iddjt30 - fr4 board for the ga20sicp12 - 263 with the on board resistance of 3.75 ? figure 27 : maximum gate resistance for safe operation of the ga20sicp12 - 263 at different drain currents using the ga03iddjt30 - fr4 board. b:2: high speed, low loss drive with boost inductor a high speed, low - loss driver with boost inductor is also capable of driving the ga20sicp12 - 263 at high - speed. it utilizes a gate drive inductor instead of a capacitor to provide the high - current gate current pulses i g,on and i g,off . during operation, inductor l is charged to a specified i g,on current value then made to discharge i l into the sjt gate pin using logic control of s 1 , s 2 , s 3 , and s 4 , as shown in figure 28 . after turn on, while the device remains on the necessary steady state gate current i g,steady is supplied from source v cc through r g . please refer to the article ?a current - source concept for fast and efficient driving of silicon carbide transistors by dr. jacek r?bkowski for additional information on this driving topology. 4 figure 28 : simplified inductive pulsed drive topology 3 ? r g = (1/ rg1 +1/rg2) -1 . driver is pre - installed with rg1 = rg2 = 7.5 ? 4 ? archives of electrical engineering. volume 62, issue 2, pages 333 ? 343, issn (print) 0004 - 0746, doi: 10.2478/aee - 2013 - 0026 , june 2013 l r g v ee v cc v ee s 1 s 2 s 3 s 4 d s g gr ga20sicp 12- 263 nov 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - modules - copack/ pg 11 of 12 c: proportional gate current driving for applications in which the g a20sicp12 - 263 will operate over a wide range of drain current conditions, it may be beneficial to drive the device using a proportional gate drive topology to optimize gate drive power consumption. a proportional gate driver relies o n instantaneous drain c urrent i d feedback to vary the steady state gate current i g,steady supplied to the ga20sicp12 - 263 c:1: voltage controlled proportional driver the voltage controlled proportional driver relies on a gate drive ic to detect the ga20sicp12 - 263 drain - source voltage v ds during on - state to sense i d . the gate drive ic will then increase or decrease i g,steady in response to i d . this allows i g,steady , and thus the gate drive power consumption, to be reduced while i d is relatively low or for i g,steady to increase when is i d higher. a high voltage diode connected between the drain and sense protects the ic from high - voltage when the driver and ga20sicp12 - 263 are in off - state. a simplified version of this topology is shown in figure 29 , additional information will be available in the future at http://www.genesicsemi.com/c ommercial - sic/sic - junction - transistors/ figure 29 : simplified voltage controlled proportional driver c:2: current controlled proportional driver the current controlled proportional driver relies on a low - loss transformer in the drain or source path to provide feedback i d of the ga20sicp12 - 263 during on - state to supply i g,steady into the device gate. i g,steady will then increase or decrease in response to i d at a fixed forced current gain which is set be the turns ratio of the transfor mer, h force = i d / i g = n 2 / n 1 . ga20sicp12 - 263 is initially turned - on using a gate current pulse supplied into an rc drive circuit to allow i d current to begin flowing. this topology allows i g,steady , and thus the gate drive power consumption, to be reduc ed while i d is relatively low or for i g,steady to increase when is i d higher. a simplified version of this topology is shown in figure 30 , additional information will be available in the future at http://www.genesicsemi.com/commercial - sic/sic - junc tion - transistors/. figure 30 : simplified current controlled pr oportional driver proportional gate current driver gate signal i g,steady hv diode sense signal output d s g gr n 2 n 2 n 1 n 3 gate signal d s g gr ga20sicp 12- 263 nov 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - modules - copack/ pg 12 of 12 section vi: package dimensions to - 263 - 7 l package outline note 1. controlled dimension is inch. dimension in bracket is millimeter. 2. dimensions do not include end flash, mold flash, material protrusions revision history date revision comments supersedes 2015/11/23 1 updated electrical characteristics 2015/05/29 0 initial release published by genesic semiconductor, inc. 43670 trade center place suite 155 dulles, va 20166 genesic semiconductor, inc. reserves right to make changes to the product specifications and data in this document without no tice . genesic disclaims all and any warranty and liability arising out of use or application of any product. no license, express or implied to any intellectual property rights is granted by this document. unless otherwise expressly indicated, genesic products are not designed, tested or authorized for use in life - saving, medical, aircraft n avigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in deat h, personal injury and/or property damage. 0.171 (4.343) 0.181 (4.597) 0.045 (1.143) 0.055 (1.397) 0.000 (0.000) 0.012 (0.305) seating plane ga20sicp 12- 263 nov 2015 latest version of this datasheet at: http://www.genesicsemi.com/commercial - sic/sic - modules - copack/ pg 1 of 1 section vii: spice model parameters this is a secure document. please copy this code from the spice model pdf file on our website ( http://www.genesicsemi.com/images/products_sic/igbt _copack/ga20sicp12- 263_spice.pdf ) into ltspice (version 4) software for simulation of the ga20sicp12 -263. * model of genesic semiconductor inc. * $revision: 2.0 $ * $date: 20- nov- 2015 $ * * genesic semiconductor inc. * 43670 trade center place ste. 155 * dulles, va 20166 * * copyright (c) 2015 genesic semiconductor inc. * all rights reserved * * these models are provided "as is, where is, and with no warranty * of any kind either expressed or implied, including but not limited * to any implied warranties of merchantability and fitness for a * particular purpose." * models accurate up to 2 times rated drain current. * * start of ga20sicp12- 263 spice model * .subckt ga20sicp12 drain gate source q1 drain gate source ga20sicp12_q d1 source drain ga20sicp12_d1 d2 source drain ga20sicp12_d2 * . model ga20sicp12_q npn + is 9.833e- 48 ise 1.073e- 26 eg 3.23 + bf 88 br 0.55 ikf 5000 + nf 1 ne 2 rb 3.09 + irb 0.006 rbm 0.101 re 0.005 + rc 0.035 cjc 910e- 12 vjc 3.2509 + mjc 0.51624 cje 2.77e- 9 vje 2.896 + mje 0.472 xti 3 xtb - 1.5 + trc1 8.500e- 3 vceo 1200 icrating 20 .model ga20sicp12_d1 d + is 5.48e- 17 rs 0.03214547 n 1 + ikf 1000 eg 1.2 xti 3 + cjo 1.15e- 09 vj 0.44 m 1.5 + fc 0.5 tt 1.00e- 10 ibv 1.00e- 03 .model ga20sicp12_d2 d + is 1.54e- 13 rs 0.23 n 3.941 + ikf 19 eg 3.23 xti 0 + fc 0.5 tt 0 ibv 1.00e- 03 .ends * end of ga20sicp12- 263 spice model |
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